The present invention relates to a voltage amplifier for amplifying input signals having a variety of signal amplitudes, such as a signal obtained through current/voltage conversion of an output current from a photodiode that receives an optical signal from an optical fiber, to a constant amplitude in optical communications systems such as a PDS Passive Double Star) optical subscriber system.
In recent years, vigorous studies have been carried out on optical subscriber systems in order to realize future FTTH (Fiber To The Home) services. However, the introduction of an optical fiber, which has extremely large transmission capacity, to households presents the problem that it is less cost effective than conventional metallic cables. Under this circumstance, the PDS optical subscriber system is considered promising from the viewpoint of cost effectiveness, since it has enabled a two-way communications service to a plurality of subscribers by splitting a single optical fiber supplied by the station side.
In such an optical communications system, as the distances between individual households and the station differ from one another, so do the optical fiber transmission distances. The attenuation of light also varies between them, and signals obtained through photoelectric conversion at an optical link section of a light receiving device, are turned into voltage signals having a variety of amplitudes, including signals having a very small amplitude and signals having a large amplitude. In order to extract clocks and data from these voltage signals, it is necessary to amplify the signals to voltage signals having a constant amplitude of a level at which digital processing is possible.
However, if the gain is set high for input signals having a small amplitude when amplifying the signals with a commonly used amplifier, an offset causes saturation of the output, or the output signal saturates and greatly distorts the waveform when signals having a large amplitude are input, thereby making it impossible to extract clocks and data.
In view of this, there has been proposed an amplifying circuit as disclosed in Japanese Laid Open Patent Publication No. 6-310967. In the configuration of this amplifying circuit, a peak value and a bottom value of an input signal are each detected and held, and an intermediate voltage value of these values and the input signal are input to an amplitude limiting amplifier.
The amplifying circuit proposed by the above-mentioned publication, however, requires two peak detecting circuits, namely, a peak value detecting-and-holding circuit and a bottom value detecting-and-holding circuit, resulting in increased power consumption. Furthermore, it also requires a circuit for dividing the output voltages of the above-mentioned circuits. In order to increase the response speed of this voltage dividing circuit, it is necessary to decrease the value of the resistance used for the voltage division, promoting the increase of power consumption further.
Additionally, a time period in which the intermediate voltage of the peak value and the bottom value is generated and stabilized is the sum of a time period in which the output of each of the peak value detecting-and-holding circuit and the bottom value detecting-and-holding circuit is stabilized and a time period in which the output of the voltage dividing circuit is stabilized, so that there is the problem of a significant time delay.
Therefore, with the foregoing in mind, it is an object of the present invention to provide a reference voltage generating circuit with low power consumption that is excellent in the high-speed response performance, and a voltage amplifier that uses the same to amplify input signals having a variety of signal amplitudes to a constant amplitude.
In order to solve the above-mentioned object, according to the present invention, a reference voltage between the maximum peak value and the minimum peak value of an input signal is automatically generated at the time when these peak values are detected.
More specifically, the present invention provides a reference voltage generating circuit wherein a signal is input, a maximum peak value or minimum peak value of the input signal in a first period is detected and held as a first peak value, a minimum peak value or maximum peak value of the input signal in a second period different from the first period is detected and held as a second peak value, and a voltage between the first peak value and the second peak value is output as a reference voltage.
According to the present invention, the reference voltage generating circuit comprises: a first capacitor; and a capacitor string comprising a cascade connection of a second and a third capacitor, wherein: the first peak value is held in the first capacitor, and a voltage difference between the first peak value and the second peak value is held in the capacitor string; and a voltage held in the second capacitor is added to a voltage held in the first capacitor, and the voltage thus obtained is output as a reference voltage.
According to the present invention, in the reference voltage generating circuit, a capacitance value of the second capacitor and a capacitance value of the third capacitor are equal.
According to the present invention, in the reference voltage generating circuit, the first capacitor and the capacitor string are cascade-connected.
According to the present invention, in the reference voltage generating circuit, a capacitance value of the first capacitor is sufficiently larger than the capacitance values of the second and the third capacitors.
The present invention also provides a reference voltage generating circuit comprising: a first capacitor; a capacitor string comprising a cascade connection of a second and a third capacitor; a voltage/current converting circuit for outputting a current corresponding to a voltage difference between two input voltages input to two input terminals; a unidirectionally-conductive element for passing a current only in one direction; a buffer circuit; and first and second reset circuits, wherein: an output terminal of the voltage/current converting circuit is connected to one end of the unidirectionally-conductive element; the other end of the unidirectionally-conductive element is connected to one end of the capacitor string and to an input terminal of the buffer circuit; the other end of the capacitor string is connected to one end of the first capacitor; a predetermined voltage is applied to the other end of the first capacitor; an output terminal of the buffer circuit is connected to one input terminal of the voltage/current converting circuit, and a signal is input to the other input terminal of the voltage/current converting circuit; the first reset circuit discharges an electric charge of the first capacitor; and the second reset circuit discharges electric charges of the second and third capacitors constituting the capacitor string.
The present invention provides a reference voltage generating circuit comprising: a voltage generating circuit for generating a predetermined voltage; and a capacitor string comprising a cascade connection of two capacitors, wherein: one end of the capacitor string is connected to an output terminal of the voltage generating circuit, and a peak value of an input signal is detected and held on the other end of the capacitor string; and a voltage at a node connecting the two capacitors constituting the capacitor string is output as a reference voltage.
According to the present invention, in the reference voltage generating circuit, capacitance values of the two capacitors constituting the capacitor string are equal to each other.
The present invention also provides a reference voltage generating circuit comprising: a voltage generating circuit for generating a predetermined voltage; a capacitor string comprising a cascade connection of two capacitors; a voltage/current converting circuit for outputting a current corresponding to a voltage difference between two input voltages input to two input terminals; a unidirectionally-conductive element for passing a current only in one direction; a buffer circuit; and a reset circuit, wherein: an output terminal of the voltage/current converting circuit is connected to one end of the unidirectionally-conductive element; the other end of the unidirectionally-conductive element is connected to one end of the capacitor string and to an input terminal of the buffer circuit; the other end of the capacitor string is connected to an output terminal of the voltage generating circuit; an output terminal of the buffer circuit is connected to one input terminal of the voltage/current converting circuit; a signal is input to the other input terminal of the voltage/current converting circuit; and the reset circuit discharges electric charges of the two capacitors constituting the capacitor string.
The present invention provides a voltage amplifier comprising: the above-described reference voltage generating circuit; and a differential amplifying circuit for outputting an output voltage corresponding to a voltage difference between two input voltages input to two input terminals, wherein: an input signal is applied to the reference voltage generating circuit and to one input terminal of the differential amplifying circuit; and a reference voltage output from the reference voltage generating circuit is applied to the other input terminal of the differential amplifying circuit.
The present invention also provides a voltage amplifier comprising: the above-described voltage amplifier serving as a first voltage amplifying circuit; and at least one second voltage amplifying circuit, wherein: the second voltage amplifying circuit comprises a sample-and-hold circuit and a differential amplifying circuit; an input voltage to the second voltage amplifying circuit is applied to the sample-and-hold circuit and to one input terminal of the differential amplifying circuit; and an output voltage from the sample-and-hold circuit is applied to the other input terminal of the differential amplifying circuit.
According to the present invention, in the voltage amplifier, the one second voltage amplifying circuit or a plurality of cascade-connected second voltage amplifying circuits are cascade-connected in a stage subsequent to the first voltage amplifying circuit.
According to the present invention, the voltage amplifier further comprises an offset correcting circuit, wherein the offset correcting circuit is cascade-connected in a final stage.
According to the present invention, in the voltage amplifier, the offset correcting circuit comprises: a differential amplifying circuit having a first and a second differential input terminal; and a first and a second peak detecting circuit, wherein: a first and a second signals are input; a peak value of the first input signal is detected and held by the first peak detecting circuit, and the first input signal and its peak value are input as a first differential signal to the first differential input terminal of the differential amplifying circuit; and a peak value of the second input signal is detected and held by the second peak detecting circuit, and the second input signal and its peak value are input as a second differential signal to the second differential input terminal of the differential amplifying circuit.
According to the present invention, in the voltage amplifier, the offset correcting circuit comprises: a differential amplifying circuit having a first and a second differential input terminal; and a first and a second peak detecting circuit, wherein: a first and a second signals are input; the first and second input signals are input as a first differential signal to the first differential input terminal of the differential amplifying circuit, and peak values of the first and second input signals are detected and held by the first and second peak detecting circuits, respectively, and output signals of the first and second peak detecting circuits are input as a second differential signal to the second input terminal of the differential amplifying circuit.
According to the present invention, in the voltage amplifier, a response-delay circuit for delaying detection and holding of the peak values of the first and second input signals is connected to the first and second peak detecting circuits of the offset correcting circuit.
According to the present invention, the voltage amplifier further comprises a comparator, wherein the comparator is configured so as to be able to amplify a differential voltage input to the comparator to a voltage having a constant amplitude, and also to receive a control signal and fix its output voltage value.
According to the present invention, in the voltage amplifier, an output of the differential amplifying circuit is amplitude-limited.
According to the present invention, the voltage amplifier comprises: a delay circuit, wherein the delay circuit provides a time delay between a reset signal to the reference voltage generating circuit of the first voltage amplifying circuit and a control signal of the sample-and-hold circuit of the second voltage amplifying circuit.
According to the present invention, the voltage amplifier comprises a delay circuit, wherein the delay circuit provides a time delay between a control signal of first and second sample-and-hold circuits of the second voltage amplifying circuit and a reset signal for the first and second peak detecting circuits of the offset correcting circuit.
According to the present invention, the voltage amplifier comprises a delay circuit, wherein the delay circuit provides a time delay between a reset signal for the first and second peak detecting circuits of the offset correcting circuit and a control signal of the comparator.
As described above, according to the present invention, a reference voltage is automatically generated at the time when the output of the reference voltage generating circuit has been settled, so that it is possible to generate a reference voltage at higher speed than conventional configurations, in which a reference voltage is generated by dividing a detected peak voltage with a voltage divider in a subsequent stage. Furthermore, since only one peak detecting circuit is necessary, it is also possible to reduce power consumption.
In particular, according to the present invention, the first and second peak values and the reference voltage are generated with a configuration in which three capacitors, namely, the first, second and third capacitors, are provided and the capacitor holding the voltage is switched from one of the capacitors to another, so that the reference voltage is generated with a simple configuration.
According to the present invention, since the capacitance values of the second and the third capacitors are equal to each other, an intermediate voltage of the first peak value and the second peak value is generated as a reference voltage.
According to the present invention, since the first capacitor and the capacitor string are cascade-connected, it is possible to readily generate a reference voltage with low power consumption.
According to the present invention, since the capacitance value of the first capacitor is sufficiently larger than the capacitance values of the second and the third capacitors, an offset error is suppressed at a low level.
Moreover, according to the present invention, when the input signal is a constant value in a first period, the constant voltage of the input signal can be generated by the voltage generating circuit. This eliminates the need for the first capacitor and a reset signal for discharging the electric charge of this capacitor, so that it is possible to generate a reference voltage at high speed with low power consumption by using a simpler configuration.
In particular, according to the present invention, since the capacitance values of the second and third capacitors are set equal to each other, a voltage that is exactly in the middle of the output voltage of the voltage generating circuit and the voltage held as the peak is generated.
According to the present invention, an input signal and a reference voltage that is the center voltage of the amplitude of this signal are applied to the two input terminals of the differential amplifying circuit, so that the input signal is amplified with low distortion.
According to the present invention, in the second voltage amplifying circuit, a voltage is held as the reference voltage in the sample-and-hold circuit before inputting a signal, so that a signal input thereafter is amplified with low distortion in the differential amplifying circuit.
According to the present invention, one second voltage amplifying circuit or a plurality of cascade-connected second voltage amplifying circuits are additionally cascade-connected in a stage subsequent to the first voltage amplifying circuit, so that the input signal is amplified with low power consumption and high gain.
According to the present invention, since the offset correcting circuit is cascade-connected in the final stage of the voltage amplifier, it is possible to effectively cancel an offset, thereby suppressing duty ratio deterioration due to an offset at low level.
According to the present invention, it is possible to easily cancel an offset with a simple configuration.
According to the present invention, a response-delay circuit is additionally provided with the peak detecting circuits of the offset correcting circuit, so that even when there is an extraordinary peak in the first bit, it is possible to detect a normal peak value without detecting this extraordinary peak.
According to the present invention, since a differential input voltage is amplified to a voltage having a constant amplitude with the comparator, it is possible to obtain a digital signal having an amplitude of a logic level, as well as suppressing the variation or fluctuation of the output signal due to a noise and the like.
According to the present invention, since the differential amplifying circuit is configured such that its output is amplitude-limited, even input signals having a large amplitude do not saturate, making it possible to obtain an output with little duty ratio deterioration.
According to the present invention, the reset operation is first performed for the reference voltage generating circuit of the first voltage amplifying circuit in a previous stage, then for the sample-and-hold circuit of the second voltage amplifying circuit, and then for the comparator, so that it is possible to realize a stable operation, thereby obtaining a highly accurate output.